Coded decimal adder



Oct. 11, 1966 E. ULBRICH ETAL 3,278,734

CODED DECIMAL ADDER @(Sign (0) Sign (b) yes no Sign (u,b) poshive c) dk) Set K=L. Invert a and b Set K=O Form o+b=Z e) U Form u+b +c =2 Sign(2 )posifive.

yes

Invert Z' 1' Z" Set K=L. no

9) Add OLLD in all T- ofZ" =Z" h) In) Add 01.1.0 in all T of)I'. =E

yes no I) lnveriZ'" E =E LEGENDS T5 irunsfer flea ieiruds Slgn (u,b)posiiiv T transfer affected tetruds T tetruds with double transfer C)F -E {:Z' c 666...(0LLO in each te'lrod) 999... (LOOL in each tetrod)final result Fig. la

mvem'roa Egbert Ulbrich Karl voitel 8 10 Sheets-Sheet 5 Filed Sept. 5,1961 o o o o o o o o o o o o o c c o 0 0 0 0 o o o o o o o o o o o c o oo m 0 o o o o o o o o o o o 0 o o o o o o o m 0 M 0 o o o o o o o c o oo o o o a 0 o o o o o o o o o o o o o v 0 M H H H o o o o o o o o o o oo o o o o o o o w 0 O 0 0. 0 O u n O c 0 n O o o o O O H M H o o o c o oo o o n c o o o o o o c o O 0 O O O. O O O O O O O O O O O O O O o o o ou o o a o o o o o o a o o c Ewwa a WWQJJWHUHMWMMMZMMZ INVENTORS EgbertUlbrich Oct. 11, 1966 Filed Sept. 5, 1961 E. ULBRICH ETAL com) DECIMALADDER 10 Sheets-Sheet 4 Fig.

mvsurons Egbert Ulbrich Karl Voitel & Johannes Martin 1966 E. ULBRICHETAL 3,278,734

CODED DECIMAL ADDER Filed Sept. 5, 1961 10 Sheets-$heet 5 -5.75V -2DV-20V 5.75!

-1.35v -20v -1.35V

5E +13.5V -5.4 V

Fig-

INVENTORS Egberi Ulbrich K 0 rl Voi tel 8 Oct. 11, 1966 E. ULBRICH ETALCODED DECIMAL ADDER 1O Sheets-Sheet 6 Filed Sept. 5, 1961 5 789m M 5&55885 S INVENTORS Egbert Ulbrich Karl Voiie! 8 Johannes Martin ATTORNEYOct. 11, 1966 E. ULBRICH ETAL 3,278,734

CODED DECIMAL ADDER Filed Sept. 5, 1961 10 Sheets She t 7 Egbert UlbrichKarl Voitel 81 Johannes Martin Oct. 11,1966 E. ULBRICH ETAL. I 3,278,734

CODED DEGIMAL ADDER Filed Sept. 5, 1961 10 heetsheet s AC (Fig.3

l I J3 l3 171 (Fig.4)

INVENTORS Egbert Ulbrich Karl Voitel 8 Johannes Martin Oct. 11, 1966Filed Sept. 5, 1961 E. ULBRICH ETAL CODED DEGIMAL ADDER 10 Sheets-Sheet9 MD Ac 8 5 1- 3 '7 0 0 00L0 0LOL 0 00LL 0LLL 0 0000 0000 1 10 I 0 00000000 0 00LL 0LLL 2 2 L LLLL LLLL 3 0v LL00 LL 00 4 0 0LLO 0LLO 0 00LLOLLL 5 5a 0 LO0L LLOL 0 0000 0000 5b 0 00L0 0LOL '0LO0L LL0L 5d 0 00L00LOL 0 LOLL L000 0 0000 LOL0 7 0 LOLL L000 0LOLL 00L0 0 000L 0000 3 0LOLL L000 0 LL00 00L0 0 0000 0000 0b 0 L0LL L000 L 00LL LLoL 0 0000 000081: L 00LL LLOL. 0 LoLL L000 L 00LL LL0L 9 L 00LL LL0L L L000 0LOL 0oLLL 0000 10 L LL00 00L0 12 0 0LLO 0000 13 13 0 0L00 0000 0 0LLL 0000$11;

5 0 0LLO 0000 0 0000 0000 1 15 L 00LL LLOL 0 0000 0000 0 0LLO 0000 17 170 0000 0000 L 00LL LL01. 0 0LL0 0000 $1 10 0 0000 0000 L LO0L LLOL 00000 0000 186 0 0000 0000 0 0LLO 00L0 0 0000 0000 lNVENTORS EgbertUlbrich Karl Voitel 8 Johannes Martin Oct. 11, 1966 Filed Sept. 5, 1961E. ULBRICH ETAL CODED DEGIMAL ADDER 10 Sheets-Shed 10 7 MD -AC 08 1 2 73 5 U 0 00L0 0LLL LL00 LOL0 0 0000 0000 1 1b l 0 00L0 0LLL L LL00 LOL0$5 6 0 GOLD 0LLI. L LLLO LLOL 0 0000 0L00 7 7 L LLLo LL0L L LLLO L00L 00000 L000 8 80 L LLLO LLOL L LLLL 000L 0 0000 0000 01: L LLLL 000L I.LLLO LLOL L LLLL 000L 9 9 0 000L LL00 L LL00 00L0 1o 0 0000 LLLO 11 13 00000 0L00 L LL00 00L0 14 16 1. LLLL 0001. 0 0000 0000 0 0000 0LL0 17 00000 0000 L LLLL 000L 0 0000 0LL0 18b 0 0000 0000 L'LLLL mu 0 0000 0000INVENTORS Egbert Ulbrich Karl voitela Johannes Martin ATTORNEY UnitedStates Patent 3,278,734 CODED DECIMAL ADDER Egbert Ulbrich, Karl Voitel,and Johannes Martin, all of Backnang, Germany, assignors to TelefunkenPatent! verwertungs-G.m.b.H., Ulm, Donau, Germany Filed Sept. 5, 1961,Ser. No. 136,710

' 15 Claims. (Cl. 235-469) The present invention relates generally tocomputers and more particularly to such devices for adding binary codeddecimal numbers in a parallel binary arithmetic unit wherein negativeoperands are represented as complements or inversions (0 L, L- 0) of thecorresponding positive values.

It should be noted that in order to prevent confusion with decimal 1,logic ONE will be indicated as L throughout the specification andclaims.

The main object of the present invention is to provide a computerprocess for adding binary coded decimal numbers regardless of theiralgebraic signs.

Another object of the invention is to simplify this operation.

According to the present invention, when adding two positive operandsOLLO (=6) is added in each tetrad and then OLLO is subtracted in thosetetrads which did not result in a carry or transfer into the next highertetrad (carry-free tetrads). When processing two negative operands, theyare first made positive by inversion and.

then the process is carried out as with positive operands. Afterwardsthe corrected result is reinverted. When processing operands ofdifferent algebraic signs, after the addition of the two operands 0LLOis subtracted in the carry-free tetrads if the sum is positive; and ifthe sum is negative, OLLO is added in-the-tetrads where a carry hastaken place (carry-affected tetrads). The subtrac-v tion of OLLO in theindividual tetrads is preferably accomplished by inverting the totalnumber, adding OLLO in the tetrads concerned, and reinverting the totalnumber.

In a variation of the above-mentioned computing process, when adding twonegative operands, OLLO is subtracted, i.e., LOOL is added, in eachtetrad and then OLLO is added to the tetrads which have resulted in adouble carry into the next higher tetrad.

Additional objects and advantages of the present invention will becomeapparent upon consideration of the following description when taken inconjunction with the accompanying drawings in which:

FIGURE 1 is a flow diagram of the process comprising the presentinvention. I

. FIGURE la is a flow diagram of another embodiment of this process withonly the differing steps being identi- FIGURE 2 is a block diagram of aparallel arithmetic unit for a binary computer.

FIGURE 3 is an elevational view of a plugboard for the arithmetic unitfor connecting the register elements for each digit to other circuits.

FIGURE 4 is a circuit diagram of one of the networks, which is connectedto the plugboard.

FIGURES 4a-4c illustrate the legends used in the drawings to designateresistor connections, diode connections, and direct connections,respectively.

FIGURE 5 is a circuit diagram of a register element.

FIGURE 6 is a circuit diagram of a power element.

FIGURE 7 is a circuit diagram of the microprogram.

FIGURE 8 is a Boolean algebra notation of this program.

FIGURE 9 is a block diagram showing the circuit connection whenswitching chain element LS is in operation.

' and b! Set K=Ol along the no arrow.

ice

FIGURE 10 is an example of the computing steps when adding two positivenumbers.

FIGURE 11 is an example when adding one negative and one positivenumber. I

In the following description, inversion of a binary number or of abinary coded decimal number means that each 0 is converted to a L andeach L is converted to a 0. The above-mentioned computing process for adigital computer is shown as a flow diagram in FIGURE 1. In the boxeshaving a '2 at the end, the computer is to make a yes-no decision, andin the boxes having an I at the end, the computer is to carry out acommand.

In the first step, the computer decides whether or not the signs of thetwo operands are equal. This is indicated by step (a) sign (a)=(b)?. Inthe event that the signs are equal, the process follows the yes arrowwhich points to step (b) sign(a,b) positive? where the further decisionas to whether the signs are algebraicly positive or negative must bedecided. In the event that the signs are positive, the process followsthe yes arrow which points to step (0) Set K=L! Where this fact isstored in the computer by setting a bistable element K at condition L.In the event that both signs are negative, the process proceeds fromstep (b) to step (d) invert a In the step (d), a and b are to beinverted and the bistable element K is set at 0. 1

As the next step, when both signs are the same, the process proceeds tostep (e) form a+b+c=2! wherein the sum of a+b+c is formed. It should benoted that +c means that OLLO is added in all tetrads. next step (1)invert E!=2 this sum is inverted. After the inversion step the processproceeds to step (g) add OLLO in all T; of 2!=2 where OLLO is added tothe tetrads in which there was no carry. Now the result has to be againinverted if both signs were originally positive. If both were negative,the result already represents the final result. This information hasalready been stored in the bistable element K. The computer thusdetermines whether K stands at L, as indicated by step (h) K=L?. If theanswer is yes the process continues with step (i) invert 2"!=E Where thelast sum is inverted again. If the answer is no" 2 is already the result(=E).

If the two operands had different algebraic signs, firs the sum of a andb is formed. This is indicated by following the no arrow starting fromstep (a) sign (a): sign (b)? to step (k) form a+b=Z! where the sum of aand b is determined. Step (1) decides whether this sum is negative, andif so OLLO is added by step (In) in all tetrads in which there has beena transfer (T and the sum thus formed represents the final re-' sult E.If the sum is positive the process proceeds to step (n) set K=L! and thesum is inverted as in step (f). The further processing of theintermediate sum 2" is now performed in the same manner as was describedfor the steps performed when the signs of a and b are equal.

Another embodiment of carrying out the process, which is mentioned aboveis shown in FIGURE 1a, where only the steps deviating from the abovedescribed process are shown. If both signs are negative, no inversionstep is performed, but LOOL (=9) is added in all tetrads as indicated instep (d') form a+b+c!=2'. Subsequently in step (e') OLLO is added inthose tetrads T where there have been double carries.

The following description will set forth the design of a microprogramcircuit for a parallel binary computer which carries out the processdescribed. FIGURES 2, 3 and 4 shows a parallel arithmetic unit. As seenin FIGURE 2, this unit contains at least two registers, namely, an

Patented Oct. 11,1966

As the accumulator register AC, comprising the register elements Ra RaRa and a carry or transfer register UB comprising the register elementsRu Ru Ru An auxiliary register is also provided which in this case is amultiplicand register MD which is generally present in computers, andwhich comprises N register elements Rd Rd Rd Each register element ofthese registers has two inputs, which are designated by thecorresponding lower case letter with a subscript and a prime. By meansof these inputs, the register elements can be set at or L. The 0 inputsare indicated by a superscript horizontal bar. For example, the Nthelement of the MD register Rd has input d for L and d for 0.Correspondingly, the outputs of the register elements are designated bythe same character but without the prime. Thus, the outputs of elementRd are indicated d and d,,. In addition, each register element has acycle or timing input T, which is connected with a source of cycle ortiming pulses. The computer is organized in a known manner whereby theregister elements include a preliminary storage element which is set bythe inputs at 0 or L on one pulse and the information in the preliminarystorage element is transferred to the register element proper on thesubsequent cycle pulse.

FIGURE illustrates an example of a complete register element R in theform of a bistable flip-flop of the Eccles- Jordan circuit type. Thisincludes the transistors 1 and 2 which are controlled from their bases.The capacitors 3 and 4, which are charged via the inputs p and p, serveas preliminary storage elements. A source of cycle pulses is connectedwith the terminal T. If, for example, the terrninal p is at a positivepotential before a cycle pulse, the condenser 4 is first charged. On thenext cycle pulse this charge is carried to the base of transistor 2 sothat this transistor 2 now conducts and blocks transistor 1. The outputterminal 2 then has a positive potential while the output terminal p hasa negative potential. The mode of operation of such bistable elements isknown per se and therefore will not be described in further detail.

The arithmetic unit shown in FIGURE 2 further comprises a time switchingchain SK comprising the individual elements LS LS L5 which are designedin the form of power elements. Power elements are effective elementswhich, although logically representing customary conditions for aconjunction, differ electrically from other conditions in that theyprovide the total power for all connections to a conjunction and may bethought of as elements which activate or deactivate the conjunctions.This time switching chain controls the timing or sequence of theindividual commands of a microprogram. The main characteristic of thesepower elements is that they provide substantially greater power at theiroutputs S S S than the register elements, in order to control theconjunctive and disjunctive connections of corresponding registerelements which elements are generally in parallel for all N binarydigits. Conjunctive connections are those logical connections effectedby an AND circuit, i.e., all conditions must be met in order to completethe connections, and disjunctive connections are those logicalconnections effected by an OR-circuit, i.e., only one condition need bemet in order to complete the connections. Each of the power elements hasa single input S and a single output S If a positive voltage is appliedto the input, the elements remain actuated from the next cycle pulse tothe following cycle pulse, and are deactuated if the input voltage hasdisappeared by the time this latter pulse appears. To carry out thisfunction, these elements are provided with a preliminary storage elementwhich is connected with the input terminal.

In FIGURE 6, such a power element LS is shown in detail. When a positiveDC. voltage is applied to the input 8' the preliminary storage element,which is a condenser 5, is charged via a transistor 6. This charge istransferred to the transistor 7 by means of the next pulse fed to thecycle pulse input terminal T. The other transistors 8, 9 and 10 amplifythe power which is to be tapped at the output S The detailed function ofsuch a power element is not an object of the present invention and istherefore not described in further detail. Whenever a positive voltageis applied to the input S,,, a positive voltage with sufiicient powerfor controlling several logical circuits is provided at the output S inthe next cycle.

In addition to the switching chain described, the arithmetic unitcontains further power elements LA LA LA LA LA LD and LU (FIGURE 2) thefunctions of which are described in detail below. Furthermore, thearithmetic unit contains some register elements Rr ,Rr Rr which aredesigned the same as the register elements of the MD, AC and UBregisters, and the functions of which will also be described below. Inthe foregoing, only the power and register elements which are necessaryfor the special microprogram of decimal addition for practicing theinvention are set forth. The other parts of the computer have beenomitted for the sake of clarity.

In addition to the register and power elements of FIG- URE 2, thearithmetic unit comprises a number of networks wherein, for each binarydigit, the logical connections necessary for the calculating operationsare provided by means of resistances and diodes. The number of networkscorresponds to the capacity which is desired for the binary computer andone network is coordinated with each binary digit. In addition, at leastone network is provided for the algebraic sign. FIGURE 4diagrammatically shows a network that is constructed of Pertinax, forexample, or some other suitable insulating material. The front side ofthis material is provided with horizontal conductors arranged parallelto one another, while the rear side is provided with conductorsextending at right angles thereto. The ends of the horizontal conductorsare provided with plug-in devices such as plugs which fit intocorresponding sockets of a plugboard shown in FIG- URE 3.

For the sake of clarity, in FIGURE 4 the resistors are represented by adot at the corresponding intersection of the horizontal and verticalconductors. As shown in FIGURE 4a, in each case these resistors connecta horizontal conductor with a vertical conductor. Diodes connect ahorizontal conductor with a vertical conductor as indicated in FIGURE4b. In FIGURE 4 this is indicated by a diagonal line connecting the twoconductors. This diagonal has a dot at the end corresponding to theanode. In FIGURE 40, direct connections between horizontal and verticalconductors are indicated by a diagonal line having -a dot at both ends.

In FIGURE 4, legends near the ends of the horizontal conductors indicateterminals or plug-in devices which are plugged into the sockets of theplugboard which have corresponding legends. These legends indicate theterrninals of the register and power elements which are connectedthereto. It should be noted that the index n extends from 1 to N. Thus,all sockets in the board having an index n, n-l, or n+1, are separatelyconnected to the corresponding register element. On the other hand, thesockets without an index n are connected with one another for all Nboards, as shown in FIGURE 3, so that the output of the correspondingpower element acts simultaneously on all networks.

An exception to this is the socket series for A where two sockets areconnected with one another, two are skipped, and then two sockets areagain connected, etc. This series of sockets enables the arithmeticunit, which is for pure binary computation, to compute also with decimalnumbers coded in tetrads. In the arrangement shown in FIGURE 3, it isassumed that the board with the index 1 is coordinated with thearithmetic sign V with O desigating the positive sign and L designatingthe negative sign. The columns 2, 3, 4 and 5 are coordinated with thefirst tetrad T and the columns 6, 7, 8 and 9 are coordinated with thesecond tetrad T etc. The bottom row k of the plugboard corresponds to aconjunction which responds if all register elements of the carryregister UB are at 0, i.e., if the carry register is empty. Thes may beseen in FIGURE 4 when it is noted that, in each calculating unit networkthe horizontal conductor i is connected with the bottom line k via adiode and the vertical line to the extreme left.

The power elements of FIGURE 2, which have their outputs connected toeach network of the arithmetic unit via the plugboard of FIGURE 3, havethe following functions which are effected by the correspondingresistances and diodes shown in FIGURE 4.

LA., effects the connection of the conjunctions for the transfer of anumber from the MD register into the AC register;

LA holds the cyclic sum in the AC register, that is, the sum modulo 2 ofcorresponding binary digits of the numbers recorded in the AC and UBregisters, and simultaneously effects a transfer of the digits formed bythe AC and the UB registers one position to the left into the UBregister via conjunctive connections;

LA; inverts the content of the AC register, i.e., all Ls become s andall Os become Ls;

LA shifts the content of the AC register one position to the rightthereby cancelling a but maintaining al LA cancels the AC register,i.e., all elements are placed at 0;

LA effects a partial cancellation of the AC register by setting thealgebraic sign digit and the last two tetrad digits at zero while theother digits maintain their value;

LD effects a connection of the conjunctions for the.

transfer of a number from the AC register into the MD register, which isthe opposite operation performed by LA and LU efiects the connection ofthe conjunctions for the transfer of a number from the AC register intothe UB register.

The remaining individual register elements illustrated in FIGURE 2 havethe following functions:

Rr is a flip-flop which is designed like a register element of thearithmetic unit (FIGURE 5) and which stores the finish signal of thetransfer removal and makes it available. The transfer removal isfinished when UB is empty, i.e., when all its register elements Ru areat zero. This is determined by the conjunction k and stored by thesetting of Rr Rr is a similar indicator flip-flop which, for example, isset when both operands are negative.

Rr is a flip-flop which is set at L when the operation of themicroprogram is completed. Its output transmits the finish signal of theoperation to the command unit which then again has the arithmetic unitat its disposal for making further calculations.

FIGURE 7 diagrammatically shows the design of a microprogram networkwhich is constructed similar to the arithmetic unit network of FIGURE 4and which is designed for the microprogram of decimal addition whichforms the object of the present invention. The outputs S S S of the timeswitching chain are connected with the input terminals of themicroprogralm board via resistances. These outputs control the timingand the logical connections of the program generally outlined inFIGURE 1. The timing or sequence of this microprognam is shown in detailin FIGURE 8 using the Boolean algebra system of notation. The firstcolumn indicates a consecutive numbering of the states attained in theregisters and, between these numbers, indicates the functioning outputsof the time switching chain. The three following columns MD, AC and U13indicate the content of the MD register, the AC register, and the UBregister at any given time. The last column contains the logicalconnections effected by the power elements LS L3 The inputs of theregister elements (lower case letters) and of the power elements(capital letters) are indicated circuit inverts the content of the ACregister.

6 in brackets. These inputs are set when, in addition to the positiveoutput of the timeswitching chain element indicated in column 1, theconditions stated after the bracket are attained. Conjunctions are noteddirectly one after the other, while disjunctions are separated from oneanother by a v. The presence of the output voltage of the power elementof the switching chain associated therewith has not been listed again,but as a further condition it must be provided. The wiring of themicroprogram of FIGURE 7 is identical with the symbolic notation ofFIGURE 8, and the latter represents an unambiguous indication for thecircuit technician.

In order to illustrate the sequence or timing of the command, individualportions of the programs will now be explained. At the start, theoperands Z and Z are carried into the MD and the AC registers in a knownmanner by a command in the command register (not shown). The first powerelement LS of the switching chain is set at L. The row S of the chart ofFIGURE 8 indicates that three cases have to be distinguished, i.e., thecases in the right-hand column of the figure, noted by brackets and thefollowing conditions which are set olf by semicolons:

Case 1: If the two sign register elements of the AC and MD registers areat condition L (outputs a and al and if the indicator register elementRr is at 0, which it always is at the start, this indicatesthat bothalgebraic signs are negative. Then, as indicated by the bracket, Rr LAand LS are set at L at the next cycle pulse. The switching chain thusremains in the first sequence stage (8' but prepares for Case 2 (r andinitiates the inversion of Z in the AC register. The other negativeoperand Z is inverted (A' only in sequence stage 5 depending upon r rCase 2: If both signs are positive (a d or if during Case 1 theindicator flip-flop Rr has been set at L (1-5), then, as noted by thesecond bracket: the second sequence stage is prepared (8' the powerelement LU (U,,) is set which transfers the content of the AC registerinto the UB register; and the power element LA (A' is set whichsubsequently cancels the AC register. The state which is then attainedis noted in row 1a of FIGURE 8. The first operand Z remains in the MDregister, the absolute amount of the second operand Z appearsin the UBregister, and the AC register is empty.

Case 3: If Z and Z have difii'erent algebraic signs, i.e., if one of theconditions FL; d or It] d is met, then, as noted in the third bracket:the sequence stages S to S are skipped and the sequence stage S of theswitching chain (S' is prepared; the power element LU (U,,) is set,which effects the transfer of Z into the UB register; and the powerelement LA (A' is set, which effects the transfer of Z from the MDregister into the AC register.

The sequence stages S S and S of the switching chain generate the 6(OLLO) which is to be added or subtracted when the algebraic signs ofthe two operands are the same. This 6 (OLLO) is generated in each tetradof the previously cancelled AC register (row 1a). As may be seen, thisis accomplished by inverting the zeros (S by the action of LA partiallycancelling the tetrads by means of the power element LA (S and shiftingone digit to the right in each tetrad by means of the power element LA(S For better illustrating this action, the state of the circuit of thearithmetic unit in the sequence stage S is illustrated in detail inFIGURE 9. This state of the In the preceding cycle, the input S of thepower element LS has voltage applied thereto by the output of the powerelement LS The first cycle pulse switches to the power elements LS via Tso that a voltage appears at the output S This pulse also prepares thepower elements LS (next sequence stage) and LA (inversion) to switch inthrough their input terminals 8' and A' The second cycle pulse switchesin the power element LA via T so that the outputs a are now connectedwith the inputs a,, and the outputs a are connected with the inputs a'(n: 1,2,3, N) via the corresponding diades D and D which are placed intotheir conducting states by controlled action. At the third cycle pulse,the switching of the register elements Ra is carried out via theterminals T3- As early as the second cycle pulse, the power element LSof the switching chain was switched in via T' This power elementprepares to carry out the operation of cancelling the sign digit and thelast two tetrad digits by means of the power element LA (not shown), inthe third cycle.

Sequence stage S forms the sum |Z |+c, where c is a number with 6 (OLLO)in each tetrad. First, the indicator flip-flop Rr is set at Zero in eachcase so that the condition F is obtained. As noted in the first set ofbrackets for stage S this condition is maintained, and the addition of[Z and c is carried out in the AC register (A' until the transfer isremoved and the conjunction k responds (row 5a). At the next cyclepulse, this conjunction sets Rr at L and, at the same time, eifects thetransfer of Z from the MD register into the AC register, and thetransfer of lZ l-i-c from the AC register into the UB register. Furtherprocessing at sequence stage S now depends upon whether both operandswere positive (F or negative (r If both operands were negative, whichfact has been stored by setting the indicator flip-flop Rr in thesequence stage S the content of the AC register, namely the number Z isinverted (A and the sequence stage S is set (row 50). Then, in thesequence stage S the first cyclic sum 2 of lZ l, IZ I, and c is formedin the AC register while the carry bits, which have been shifted by oneposition to the left, are deposited in the UB register (n If bothoperands were positive (F the first cyclic 2 is formed in the ACregister as early as the sequence stage S under the condition r 7 andthe carry bits are deposited in the UB register. In this case theprogram immediately proceeds to sequence stage S7.

The first cyclic sum thus formed in the AC register, either in thesequence stage S (row 5d) or in the sequence stage S (row 6), must nowbe stored so that subsequently a determination may be made as to whetheror not a transfer has taken place from a tetrad. Before describing thisfunction of the microprogram circuit, the state prevailing when thesequence stage S is switched in will be summarized:

Case 1: Both operands have negative signs. The first cyclic sum 2 of |Zf and IZ I+c is held in the AC register. The indicator flip-flop Rr isset and thus has the output r L.

Case 2: Both operands have positive signs. The first cyc-lic sum 2 of Zand Z +c is held in the AC register, and the indicator flip-flop Rr isnot set and has the output T2211, S r =0.

Case 3: Both operands have different signs. The first cyclic sum 2 of Zand Z is held in the AC register. The sequence stages to S have beenskipped since in this case 0 has not been previously added.

Before the uncorrected addition result is formed by removal of thetransfers deposited in the UB register, the first cyclic sum must bestored, so as to determine the carry-free and carry-affected tetrads,respectively. This is accomplished by comparing this first cyclic sumwith the addition result which is still uncorrected regarding thepresence of pseudo tetrads. Therefore, in sequence stage S7, the firstcyclic sum 2 is stored in the MD register (D1,), and simultaneously theadding of the new carries produced by the first cyclic sum according tothe principle of progressive carry removal (A,,) is initiated. This stepis completed in the sequence stage S (S' A' As soon as the transfer isremoved, i.e., the content of the UR register is zero, the conjunction kresponds and:

with a positive sign (an) effects inversion of the uncorrected additionresult (A';); or, with a negative sign (0 sets the indicator flip-flopRr (r' In both cases, the flip-flop Rr is simultaneously set (r so that,at the next cycle pulse, the power elements LD,,, LU LA are switched inwhereby the negative of the absolute value of the uncorrected additionresult S is transferred into the MD and the UB registers and the storedfirst cyclic sum is transferred into the AC register (row 8c).

The corrections (addition or subtraction, respectively, of OLLO) stillto be made to the pseudo tetrads formed depend upon the tetrads fromwhich transfers into the next higher tetrad have or have not occurred.The presence of a transfer is determined by addition modulo 2 of thefirst cyclic sum 2 and the uncorrected addition result S. The auxiliaryresult obtained contains an L or a 0, respectively, in the lowest digitof a tetrad, depending upon whether a transfer has or has not takenplace from the lower tetrad. This is based on the fact that when thereis a transfer, the next higher binary digit changes from 0 into L orfrom L into 0 so that its sum modulo 2 equals L. If no change hasoccurred, the sum modulo 2 of 0 and 0 or of L and L is in each caseequal to 0. The number OLLO to be added is formed from the L whichappears, in a manner which will be described below.

If OLLO is to be added in carry-free tetrads, the cyclic sum 2 isinverted before the modulo 2 addition with the uncorrected additionresult so that the auxiliary result then has a L in the next binarydigit above those tetrads from which no transfer has taken place. Thisinversion is carried out in sequence stage 8,; (second bracket) if thesign digit in the AC register is positive (5 and the indicator flip-flopRr has not been set at L6 in the sequence stage S In sequence stages 8,,to S the correction number is formed from the auxiliary result by ashift to the right (A and partial cancellation (A' This correctionnumber contains OLLO in the tetrads to be corrected and 0000 in thetetrads which are not to be corrected. It is then carried into the UBregister. Then, in sequence stage S this correction number is added tothe uncorrected addition result |S'| which has in the interim beenstored in MD and was then carried back to AC (A,,) in sequence stage SThe formation of OLLO in the AC register is indicated, for one tetrad,in rows 9 to 15 of FIGURE 8 in column AC. The content of this one tetradis indicated in the brackets, and the determining binary digit is shownin front. The symbol means that the determining L or 0 occurs in thiscase, X means that L or 0 occurs at random in this case, and 0 meansthat, by a partial cancellation, a 0 stands in this case.

In sequence stage S after the addition (A',,) of the correction numberonto the uncorrected addition result IS], the content of the AC registerunder certain condition (F is inverted (A';) as soon as the transfer hasbeen removed (k At the finish, the corrected addition result S stands inthe AC register, the indicator flip-flops are set at 0 (F 73), and thesign end of operation is signalled (r by the flip-flop Rr The operationof the microprogram for decimal addition in a binary parallel computerhas been described using an example which has been kept as simple aspossible. Only the AC and UB registers need be capable of addition,while the MD register is used only as an auxiliary register. In general,in a binary computer the MD register, too, will be capable ofcomputations and, possibly, further registers will be available. In suchan event, some computing operations of the above-described program maybe combined (for example, the addition of Z +Z +c) and the computingtime may be even shorter. Thus, the circuit diagram shown in FIGURE 7and the corresponding flowsheet of FIGURE 8 do not represent the onlyrealization of the invention possible in connection with themicroprogram according to FIGURE 1. This only represents one embodimentfor which the special problem of decimal addition is provided, with asfew circuit elements as possible, without regard to other programs to becarried out with this machine. Depending upon the circuit mean-s andlogical connections which are present in the computer for otherpurposes, the network of FIGURE 7 may be correspondingly modified. Also,in the arithmetic unit according to FIGURES 2 and 4, only the circuitelements and logical circuits necessary for decimal addition are shownso that the description is not made more complex by statements which arenot necessary for understanding the invention.

FIGURES 10 and 11 show two computing examples which may be readilyunderstood with reference to FIG- URES 7 and 8. FIGURE 10 shows theaddition of two positive numbers +37=+62, and FIGURE 11 shows theaddition of one positive and one negative number +27-35=-8.

It will be understood that the above description of the presentinventionis susceptible to various modifications, changes, andadaptations, and the same are intended to be comprehended within themeaning and range of equivalents of the appended claims.

What is claimed is:

1. A computer, comprising in combination: an accumulator register; acarry register; an auxiliary register; a plurality of power elementmean-s for simultaneously applying power signals to at least severalelements of each register to carry out predetermined steps; controlnetwork means connecting said power element means with said registersand providing a predetermined connection forming a circuit meanstherebetween for each of a plurality of sequence stages, eachpredetermined connection being in a ditferent portion of said networkmeans; sequence switching chain means adapted to receive timing pulsesand individually actuating the predetermined connections, said networkmeans being arranged to cause addition of decimal numbers having theirdigits binary coded in tetrads to form operands which are summands whenready for an addition process whether previously processed or not,-thecircuit means defining said network means including: first circuit meansfor controlling said power element means to selectively invert thecontent of a register when it represents a negative binary number sothat it represents the corresponding positive number; second circuitmeans for controlling said power element means to add two binary numbersin two registers to form a first cyclic sum exclusive of. all carriesand for adding the carries to said sum to form an uncorrected additionresult; and third circuit means for controlling said power element meansto add said first cyclic sum and said uncorrected addition result to forman auxiliary number in one of said registers which indicates in thelowest digit of each of its tetrads whether a transfer from the nextlower tetrad has taken place during formation of the uncorrectedaddition result.

2. A computer, comprising, in combination: an accumulator register; acarry register; an auxiliary register; a plurality of power elementmeans for simultaneously applying power signals to at least severalelements of each register to carry out predetermined steps; controlnetwork means connecting said power element means with said registersand providing a predetermined connection forming a circuit meanstherebetween for each of a plurality of sequence stages, eachpredetermined connection being in a different portion of said networkmeans; sequence switching chain means adapted to receive timing pulsesand individually actuating the circuit means, said network means beingarranged to cause addition of decimal numbers having their digits binarycoded in tetrads trolling said power element means for selectivelyinverting the content of a register when it represents a negative binarynumber so that it represents the corresponding positive number; secondcircuit means for controlling said power element means for adding in abinary manner the content of two registers according to the principle ofprogressive carry removal; and third circuit means for controlling saidpower element means for determining those tetrads in which a carryoccurred, by adding the first cyclic sum of the binary addition beforethe carry removal, to the sum after the carry removal.

3. In a decimal addition control section of a parallel computer forcontrolling arithmetic registers formed of binary elements, the controlsection including means for inverting all binary positions of negativeoperands in the registers to represent them as corresponding positivenumbers, an adder for adding in a binary manner the contents of twoarithmetic registers according to the principle of progressive carryremoval to form a first cyclic sum which is free of carries, and to forman uncorrected addition result which includes the carries, and means forforming correction numbers in an arithmetic register for selectivelyprocessing numbers coded in binary tetrads whose operands are arrangedso that a decimal carry appears as a tetrad carry, the improvementcomprising means for comparing the first cyclic sum of the binaryaddition with the uncorrected addition result to form in dependence uponthe comparison a correction number in the content of one of saidregisters, and said correction number forming means being actuatedresponsive to a predetermined binary condition in said one register inthe lowest binary position of the respective next higher tetrad from theone in which the carry occurred as an indication of a carry.

4. The improvement in a decimal addition control section as defined inclaim 3 wherein the operands in two of the registers have negative signsand comprising means responsive to the two negative signs of theoperands for subtracting OLLO in each tetrad of one of the operands saidsign responsive means being arranged to thereafter add OLLO in thosetetrads which have had a carry twice.

5. The improvement in a decimal addition control section as defined inclaim 3 wherein the decimal numbers have their digits encoded in thenatural binary code (84-2-1), and said correction number forming meansbeing arranged to form a correction number of OLLO for each tetradrequiring correction.

6. The improvement in a decimal addition control section as defined inclaim 5 comprising means for placing said one register into thepredetermined binary condition in all binary positions, after which themeans for forming correction numbers (OLLO) in all tetrads becomeseffective and prepares for the addition of decimal 6 in each tetrad.

7. The improvement in a decimal addition control section as defined inclaim 3 comprising means for adding ()LLO in each tetrad of a binarynumber when required for addition.

8. The improvement in a decimal addition control section as defined inclaim 5 comprising means for adding OLLO in each tetrad of a binarynumber when required for addition.

9. In a parallel arithmetic unit of a computer for adding decimalnumbers whose digits are binary coded in tetrads and wherein negativebinary numbers are represented by inverting all binary digitsrepresenting the corresponding positive number, the unit including aplurality of registers formed of elements which represent binary digits,the improvement comprising means for adding two binary numbers in theregisters to form in one register a first cyclic sum which omits carriesand for then forming an uncorrected addition result by adding thecarries; and means for comparing the lowest digit of each tetrad of thefirst cyclic sum with the similar digits of the tetrads of theuncorrected addition result to determine those tetrads in which a carryoccurred.

10. The improvement in a parallel arithmetic unit as defined in claim 9comprising means for forming a correction number in dependence upon theappearance of a carry in the tetrad during addition.

11. The improvement in a parallel arithmetic unit as defined in claim 10comprising means for adding said correction number to the uncorrectedaddition result to thereby correct the addition result.

12. The improvement in a unit as defined in claim 9 wherein saidcomparing means is arranged to form an auxiliary number by adding thefirst cyclic sum and the uncorrected addition result, which auxiliarynumber thus has an L in the lowest binary digits of those tetrads intowhich a carry has moved and a O in the lowest binary digits of thosetetrads into which no carry has moved, and further comprising means forforming a correction number from the auxiliary number which correctionnumber includes a first correction tetrad in those tetrads of theauxiliary number where an L appears and a second correction tetrad inthose tetrads of the auxiliary number where an appears.

13. The improvement in a unit as defined in claim 12 comprising meansfor adding said correction number to said uncorrected addition result toform a corrected addition result.

14. The improvement in a unit as defined in claim 12 wherein saidcorrection number forming means is arranged to form OLLO as the firstcorrection tetrad and 0000 as the second correction tetrad.

15. In a parallel arithmetic unit of a computer for adding decimalnumbers in binary coded tetrad form which uses complementing and thusmay need correction of addi- 1 addition result; and third means forcausing addition of said first cyclic sum and said uncorrected additionresult to form an auxiliary number which indicates in the lowest digitof each of its tetrads whether a transfer from the next lower tetrad hastaken place during formation of the uncorrected addition result.

References Cited by the Examiner UNITED STATES PATENTS 2,947,479 8/1960Sclmer 235-169 2,989,237 6/1961 Duke 235--169 2,991,009 7/1961 Edwards23s 169 OTHER REFERENCES IBM Reference Manual 1401 Data ProcessingSystem, 1961.

IBM 650 Data Processing System Bulletins, 1958-59.

MALCOLM A. MORRISON, Primary Examiner. WALTER W. BURNS, JR., ROBERT C.BAILEY,

. Examiners.

B. D. REIN, M. J. SPIVAK, Assistant Examiners.

1. A COMPUTER, COMPRISING IN COMBINATION: AN ACCUMULATOR REGISTER; ACARRY REGISTER; AN AUXILIARY REGISTER; A PLURALITY OF POWER ELEMENTMEANS FOR SIMULTANEOUSLY APPLYING POWER SIGNALS TO AT LEAST SEVERALELEMENTS OF EACH REGISTER TO CARRY OUT PREDETERMINED STEPS; CONTROLNETWORK MEANS CONNECTING SAID POWER ELEMENT MEANS WITH SAID REGISTERSAND PROVIDING A PREDETERMINED CONNECTION FORMING A CIRCUIT MEANSTHEREBETWEEN FOR EACH OF A PLURALITY OF SEQUENCE STAGES, EACHPREDETERMINED CONNECTION BEING IN A DIFFERENT PORTION OF SAID NETWORKMEANS; SEQUENCE SWITCHING CHAIN MEANS ADAPTED TO RECEIVE TIMING PULSESAND INDIVIDUALLY ACTUATING THE PREDETERMINED CONNECTIONS, SAID NETWORKMEANS BEING ARRANGED TO CAUSE ADDITION OF DECIMAL NUMBERS HAVING THEIRDIGITS BINARY CODED IN TETRADS TO FORM OPERANDS WHICH ARE SUMMANDS WHENREADY FOR AN ADDITION PROCESS WHETHER PREVIOUSLY PROCESSED OR NOT, THECIRCUIT MEANS DEFINING SAID NETWORK MEANS INCLUDING: FIRST CIRCUIT MEANSFOR CONTROLLING SAID POWER ELEMENT MEANS TO SELECTIVELY INVERT THECONTENT OF A REGISTER WHEN IT REPRESENTS A NEGATIVE BINARY NUMBER SOTHAT IT REPRESENTS THE CORRESPONDING POSITIVE NUMBER; SECOND CIRCUITMEANS FOR CONTROLLING SAID POWER ELEMENT MEANS TO ADD TWO BINARY NUMBERSIN TWO REGISTERS TO FORM A FIRST CYCLIC SUM EXCLUSIVE OF ALL CARRIES ANDFOR ADDING THE CARRIES TO SAID SUM TO FORM AN UNCORRECTED ADDITIONRESULT; AND THIRD CIRCUIT MEANS FOR CONTROLLING SAID POWER ELEMENT MEANSTO ADD SAID FIRST CYCLIC SUM AND SAID UNCORRECTED ADDITION RESULT TO FORMAN AUXILIARY NUMBER IN ONE OF SAID REGISTERS WHICH INDICATES IN THELOWEST DIGIT TO EACH OF ITS TETRADS WHETHER A TRANSFER FROM THE NEXTLOWER TETRAD HAS TAKEN PLACE DURING FORMATION OF THE UNCORRECTEDADDITION RESULT.